 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| . . . . .,. .,,f,i .:. , ,.:. :,; ri, ,. ., . ., ,, :,+:. ? ,? . . . . . ...4.,, >.. .s, ,.. c .,. , ,. $ . . . , , . s .,, ...,..., ! .,,.,..,,.. : ..?,>.... . . . . . . . . . . ,., ,,, . . . . . . . . . . . . ., ., .,,.,, ,,, ,, . . . . . . order this document motorola by br5091d - semiconductor technical data .? 3 mc68882 .?.,., :,, .:..$ 1. .,. : floating-point coprocessor $. :::? ? :?:~.+i ?! ::,., ,, \,}txi\\/.. .,1., ?< .:.:,. - ..,.3 >ii}}. ,i. . . . . . . ,;.:, the mc68882 floating-point coprocessor fully implements the ieee standard for binary floatin~_+??,i~?c point arithmetic (ansi-ieee standard 754-1985) for use with the motorola m68000 family of ,,~f@&~i$ processors. an upgrade of the mc68881, it is pin and software compatible with an optimiz$d ~~$~ interface providing in excess of 1.5 times the performance of the mc68881. it is implem~~~,, ui;ng vlsi technology to give systems designers the highest possible functionality in a ph~:w&~&mali device. .!.} ~,,,* .,,,* \$.i,,, ,., >$ intended primarily for use as a coprocessor to the mc68020 or mc68030 32-bi~,~$&@?rocessor unit (mpu), the mc68882 provides a logical extension to the main mpu integer ~~$~~rocessing capabilities. this extension is achieved by providing a very high performan~~oatlng-point arith- metic unit and a set of floating-point data registers which are analogoust$~~t~ &se of the integer data registers. the mc68882 instruction set is a natural extension of a~j $afi~r members of the m68000 family, and it supports all of the addressing modes of the ~$?~~~. due to the flexible bus interface of the m68000 family, the mc68882 can be used wj~~ ari~,of the mpu devices of the m68000 family and as a peripheral to non-m68000 processors{,{~~ :&+, the major features of the mc68882 are: .,$>. . *), $ >. .:.?: . :;:,>..+ . . l eight general purpose floating-point data register% ?p~m.8?tipporting a full 80-bit extended !,,,*..l,k*, ,,**. precision real data format (a 64-bit mantissa plus ~~,~~ bit, and a 15-bit signed exponent). l a 67-bit arithmetic unit to allow very fast cal$ula~~ons~ with intermediate precision greater ? -~, than the extended precision format. .3*$;; . . ,j ? ?:*\. . a 67-bit barrel shifter for high-speed s~jfl~~b d~erations (for normalizing etc.). o special purpose hardware for high-#~~&k~?&nversion of binary real memory operands to and from? the internal extended forma~j~$,,~#> . reduced coprocessor interfac$~~wad to increase throughput. . forty-six instructions, includ~n@~~5jarith metic operations. ~,, \ ,...>.{,., ?~. . full conformation to the.#~$~}fee 754 standard, including all requirements and suggestions, .?:?!.., . support of functionsa@?%+,@#ned by the ieee standard, including a full set of trigonometric and transcendenta~, f&ct~ns, : t ?.?:* w, .,:s l seven data type$$.?b~e, word and long word integers; single, double, and extended precision ~$% ,:+ real number$),$ndp-acked binary coded decimal string real numbers. l twenty-t~t~&$,~~tants available in the on-chip rom, including n, e, and powers of 10, l virtual @&@@ry/machine operations. l effi~~<#~~echanisms for procedure calls, context switches, and interrupt handling. . ..f\. . q&fic&~~ent instruction execution with the main processor. ,4*j&qqlurrent instruction execution of multiple floating-point instructions. . ?+: ~:,$ ,~, ?:%., use with any host processor, on an 8-, 16-, or 32-bit data bus. .,,,,:., *i!<* $fi~: ~>+~~$.il> y}i:,,,, $ i*> . . . > ,. ;7 :?, ?:.? this document contains information on a new product. specifications and information herein are subject to change without notice. @ motorola - @motorola inc., 1988 brw/rev. 3 . . . . . . . . . ,. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
the coprocessor concept hardware overview the mc68882 functions as a coprocessor in systems the mc68882 is a high performance floating-point de- where the mc68020 or mc68030 is the main processor vice designed to interface with the mc68020 or mc68030 via the m68000 coprocessor interface. it functions as a as a coprocessor. this device fully supports the mc68020 ,p peripheral processor in systems where the main proces- or mc68030 virtual machine architecture and is imple- p sor is the mc68000, mc68008, or mc68010. \.; mented in hcmos, motorola?s low power, small geom- the mc68882 utilizes the m68000 family coprocessor etry process. this process allows cmos and hmos (high interface to provide a logical extension of the mc68020 density nmos) gates to be combined on the sa,,~<~~evice. or mc68030 registers and instruction set in a manner cmos structures are used where speed a~@, l~~,~ower which is transparent to the programmer. the program- is required, and hmos structures are use~, w%re mini- mer perceives the mpu/fpcp execution model as if both . ::,t. ~.,;.i. + ~$~ mum silicon area is desired. using t~,~ w&whology in- devices are implemented on one chip. a fundamental ..,,.?~> creases speed performance whi~g%~!$g low power goal of the m68000 family coprocessor interface is to consumption, yet still confines th~?~~~~~~1 to a reason- provide the programmer with an execution model based ? ~.s,~;. ,?..t+~ ably small die size. ., ,, j, ,?.j-,$\\ i..\.. !~ ?k upon sequential instruction execution by the mc68020 , *~-. the mc68882 can also qf ~~,$as a peripheral pro- or mc68030 and the mc68882. for optimum perform- cessor in systems where t@@~~c68020 or mc68030 is not ante, however, the coprocessor interface allows concur- the main processor (e,&};,w&ooo, mc68008, mc68010). rent operations in the mc68882 with respect to the the configuration o~$~ ,@68882 as a peripheral pro- mc68020 or mc68030 whenever possible. in order to sim- cessor or coprocqs$@~?m#y be completely transparent to plify the programmer?s model, the coprocessor interface ~,..s ,,, ?,~ ? user software (i.e.;%~~?%ame object code maybe executed is designed to emulate, as closely as possible, non-con- in either co~~$~::atfon). current operation between the mc68020 or mc68030 and the ar~&$,~~?re of the mc68882 appears to the user the mc68882. as a lo~i~.,1, e~tension of the m68000 family architecture, the mc68882 is a non-dma type coprocessor which beca~$@o~the coupling of the coprocessor interface, the uses a subset of the general purpose coprocessor inter- ~~fi80?* or mc68030 programmer can view the mc68882 face supported by the mc68020 or mc68030. features of .,.~eg$~ters as though the registers are resident in the the interface implemented in the mc68882 are as follows: #?~68020 or mc68030. thus, a mc68020 or mc68030 and ? ?$~e~ mc68882 device pair functions as one processor with . the main processor(s) and mc68882 communicat~~~~jw? via standard m68000 bus cycles. ~**. ~ ~ eight integer data registers, eight address registers, and .!> eight floating-point data registers supporting seven float- . the main processor(s) and mc68882 co.~muti:i- ing-point and integer data types. cations are not dependent upon the a~@:a&cture the mc68882 programming model is shown in figures of the individual devices (e.g., instruc@~$~ip&s or 1 through 6 and consists of the following: caches, addressing modes). v;> !]*q, ?..i. ~).:t.x, .* , ?:. +f{?i,~ l the main processor(s) and mc6@~~~@ay operate l ,?~.!.. . ~?x$:?~kl, ,. ~\ at different clock speeds. ~:.,?..:,.. {,m ?+< .?,$:,,, 7* ????.: l mc68882 instructions util,i~~,a$~~ddr essing modes provided by the main @#o<$#&or. ~:+ ~? ~\;~, ., *,*$ e l all effective addreqqb~~q?y%calcu lated by the main processor at th~t~~~si~ of the coprocessor. . . ,.. - eight 80-bit floating-point data registers (fpo-fp7). these registers are analogous to the integer data registers (do-d7) and are completely general pur- pose (i.e., any instruction can use any register). a 32-bit control register that contains enable bits for each class of exception trap, and mode bits to set the user-selectable rounding and precision modes. a 32-bit status register that contains floating-point condition codes, quotient bits, and exception sta- tus information. a 32-bit instruction address register that contains the main processor memory address of the last floating-point instruction that was executed. this address is used in exception handling to locate the l all data tran~fdxk$:~~e performed by the main pro- cessor at ~~?~we~uest of the mc68882. .*:\, i j+p, ,\:t l l overla~@ ft?bncurrent) instruction execution en- han~,~~?~bughput while maintaining the pro- g&~t@~*~r?s model of sequential instruction ~f3%$bnt ion, l ,,:,~?~~~~~dprocessor detection of exceptions which require ? ,j:gt, ... . . . . . a trap to be taken are serviced by the main pro- 8::?i\ij..,tj?~. ..:. .$,,>9. . . cessor at the request of the mc68882. ~lt~. instruction that caused the exception, .;. > l support of virtual memory/virtual machine sys- the connection between the mc68020 or mc68030 and terns is provided via the fsave and frestore the mc68882 is a simple extension of the m68000 bus instructions. interface. the mc68882 is connected as a coprocessor to l up to eight coprocessor may reside in a system the mc68020 or mc68030, and the selection of the mc68882 is based on a chip select which is decoded from simultaneously. multiple coprocessor of the same the mc68020 or mc68030 function codes and address type are allowed. bus. figure 7 illustrates the mpu/coprocessor configu- . systems may use software emulation of the ration. mc68882 without reassembling or relinking user as shown in figure 8, the mc68882 is internally divided ,~, ,. -, software. into three processing elements: the bus interface unit ?./ motorou m~ 2 brw/rev. 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 7 i fpo i i t \ i i i , r i fp1 fp2 fp3 floating point fp4 data registers fp5 ~ rounoing mooe: 00 to nearest 01 toward zero 10 toward minus infiniw 11 toward plus infiniv rounding precision: 00 extended 01 single 10 double 11 (undefineo, reserveo) figure 3. mode control b~e mc- motorom brw/rev, 3 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 31 30 29 2a 27 26 25 24 [ o n z i nan not a number or unordered lnfinl~ zero negative figure 4. condition code b~e 23 22 21 20 19 la 17 16 i s quotient 1 i figure 5, quotient b~e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . (biu), the conversion unit (cu), and the arithmetic proc- cycle. (the function codes are generated by the m68000 essing unit (apu). the biu communicates with the family processors to identify eight separate address mc68620 or mc68030, the cu performs data conversion spaces.)? thus, the memory-mapped coprocessor inter- for binary real data formats, and the apu executes all face registers do not infringe upon instruction or data mc68882 instructions. address spaces. the mc68020 or mc68030 places a co- the biu contains the coprocessor interface registers (cirs). in addition to these registers, the register select processor id field from the coprocessor instruction onto three of the upper address lines during coprocessor ac- and dsack timing control logic is contained in the biu. cesses. this id, along with the cpu address space func- finally, the status flags used to monitor the status of tion code, is decoded to select one of eight coprocessor communications with the main processor are contained in the system. ~ ~~~.~l, in the biu. since the coprocessor interface protocol is ba~~wlely the cu contains special purpose hardware that per- on bus transfers, the protocol is easily ernu~?~q~~y soft- forms data format conversions between binary real data ware when the mc68882 is used as a perl,~~:~~ktiith any formats to and from ?the internal extended format. the processor capable of memory-mapped @+@yat an m68000 cu relieves the apu of a significant work load and allows style bus. when used as a periphe$$.@r@ssor with the the mc68882 to execute data movement and preparation 8-bit mc68008, the 16-bit mc68,r{:~$r?he .mc68010, all functions concurrently with arithmetic and transcenden- mc68882 instructions are trapp~$:$ the main processor tal calculations, to an exception handler at g$$cut?~n time. thus, the soft- the eight 80-bit floating-point data registers (fpo-fp7) ware emulation of the c~~~~~$~or interface protocol can and the 32-bit control, status, and instruction address be totally transparent%~~:t~&wser. the mc68882 can pre- registers (fpcr, fpsr and fpiar) are located in the apu. vide a performancetw~~.@ for mc68000-based designs in addition to these registers, the apu contains a high- by changing the ?t~%~@?*processors to the mc68020 or speed 67-bit arithmetic unit used for both mantissa and mc68030. th,~~pftmre migrates without change to the exponent calculations, a barrel shifter that can shift from next gener&k$&#$eq uipment using the mc68020 or 1 bit to 67 bits in one machine cycle, and rom constants mc6803@s??:?jw? (for use by the internal algorithms or user programs). sin@?j%&$s is asynchronous, the mc68882 need not the control section of the apu contains the clock gen- ru~.at~g same clock speed as the main processor. total erator, a two-level microcode sequencer, the microcode ,j,~$&~~m performance may therefore be customized. for a rom, and self-test circuitry. the built-in self-test capa- : weti cpu performance requirement, the floating-point bilities of the mc68882 enhance reliability and ease man- s+~&.$@?iformance can be selected to meet particular price/ ufacturing requirements; however, these diagnost~~~%k~ performance specifications, running the mc68882 at functions are not accessible outside of the special test ?t slower (or faster) clock speeds than the mpu clock. ,, s~i;,y+,.>~. all communications between the mc68@~~ofwc68030 and the mc68882 occur via standard m@~~q:@>amily bus transfers, the mc68882 is design,~t~~~~~erate on 8-, 16-, or 32-bit data buses. :f},\, .*7. ~: >~$iy, .\\<.. p? the mc68882 contains a nu@b#~.~coprocessor inter- face registers (cirs) that ar~.~~r$ised in the same man- ner as memory by the rnai~~~~essor. the m68000 family coprocessor interface.r$ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,~,f .$? : .\}$ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .* .**,.,* ................................. ........................ \ .+. ?., !,: i+j ?$<. ~ :<,,,.* ,,:$? apu .,. s,, .,:>, ? i clk ! biu f built in self test registers control cir i .- 1 restore cir u save cir respowe cir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . response pla t aa a. t status flags -1 nrom , i 1 l - command/condition cir h ,!, ! .,..,), ,t!, .*,, .?.%$!,? .l.~~:~ f<, ..,, 1 4 .,>, ?) s, d, x format .,,, ,,\:{.? conversion l~lc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . @?n figure 8. mc68882 simplified block diagram ,, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ,, . . . ... ..,. . ,. since the coprocessor interface is based solely upon bus cycles (to and from cpu space) and the mc68882 is never a bus master, the mc68882 can be placed on either the logical or physical side of the system memory man- 5% agement unit in an mc68020-based system. since the -?< ..-y memory management unit of the mc68030 is on-chi~, the mc68882 is-always on the physical side of the mern~ ory management unit in an mc68030 system. the virtual machine architecture of the mc68020 or mc68030 is supported by the coprocessor intetiace and the mc68882 through the fsave and frestore instruc- tions. if the mc68020 or mc68030 detects a page fault and/or a task time out, the mc68020 or mc68030 can force the mc68882 to stop whatever operation is in progress at any time and save the mc68882 internal state in mem- ory, during the execution of a floating-point instruction, the mc68882 can stop at predetermined points as well as at the completion of the instruction. the size of the saved internal state of the mc68882 is dependent upon the state of the apu at the time the fsave is executed, if the mc68882 is in the reset state when the fsave instruction is received, only one word of state is transferred to memory, which may be exam- ined by the operating system to determine that the co- processor programmer?s model is empty, if the coprocessor is in the idle state when the save instruction is received, only a few words of internal state are trans- ferred to memory. if executing an instruction in the busy potentially fully concurrent and, therefore, can be com- pletely executed during the execution of a previous in- struction. the mc68882 also has a more optimized coprocessor interface than the mc68881. if an arithmetic instruction has data formats of single, double or extended, the dial- ogs are designed to increase the potential overlap with subsequent instructions, this overlap can significantly decrease the effective instruction execution time. double precision rga~~~~n? extended precisi~~,~<$pix) packed decimal?t~$@~?real (p) the capital letter<~$$~%ined in parentheses denote suf- fixes added .~d}$~:troctions in the assembly language source spw~l@~~fhe data format to be used. *? .~y. ,$ $*,,, lnte~~:~a$a formats ~~e t~be integer data formats (byte, word, and long state, it may be necessary to save the entire internal state ,,,~~oral. are the standard twos complement data formats of the machine, instructions completing execution in less , $,sd$ported in the m68000 family architecture. whenever time than it takes to save the larger state in mid-instrucl~c?~~~c, ?&~ integer is used in a floating-point operation, the in- tion are allowed to complete execution and then save the ?i+i, ??? ?????????tiger is automatically converted by the mc68882 to an idle state, thus, the size of the saved internal state is kepl extended precision floating-point number before being to a minimum. the ability to utilize several inter~~y, state used. for example, to add an integer constant of five to sizes greatly reduces the average conte?xt switch~~g~tie. the number contained in ?floating-point data ?register 3 the frestore instruction permits reloa~i?k~~k%n in- (fp3), the following instruction can be used: ternal state that was saved earlier and co~~~q.~ any op- fadd.w #5,fp3 eration that was previously suspende~. ~~,~&~store of (the motorola assembler syntax ?#? is used to the null state frame re-establishes d~~b$~@pister values, denote immediate addressing.) a function identical to the mc68w ~rdware reset, ,\l: ~, ..::,** \~\> the ability to effectively use integers in floating-point ,. :~$~. mc68882 performance ~~@@ements operations saves user memory since an integer repre- ~:\., the high performanceko$:~h$imc68882 is the result of sentation ofa number, if representable, is usually smaller than the equivalent floating-point representation. the mc68882?s abilty $* ~~cute multiple floating-point instructions concu,$$ent?~gf~he direct result of concur- floating-point data formats rency is to utilize$~~~~rithmetic processing unit (apu) more efficient~,{b~~?@ &creasing its idle time. the floating-point data formats, single precision (32- when th~;~,t*82 receives an instruction, the biu, bits) and double precision (64-bits), are defined by the along wit~~@~~@u, can initiate the instruction, fetch the ieee standard. these data formats are the main floating- necesww ~erands, and convert them to the internal point formats and should be used for most calculations extq,~$~~,.,$rmat even though the apu is busy complet- involving real numbers, table 1 lists the exponent and ins~s%s~ution of a previous instruction. although the mantissa size for single, double, and extended precision, t&&~81 can only instruct the main processor to wait if the exponent is biased, and the mantissa is in sign and ~&??~pu is busy, the mc68882 cu can proceed with the magnitude form. since single and double precision re- n~xt instruction. when the apu is finally ready to perform quire normalized numbers, the most-significant bit of the the calc(~lation. it can dn sn imm~diatelv without incur- mantissa is implied as a one and is ndt included, thus ., -------- -- !...,,,. ring delav due to data movement and preparation func- giving one extra bit of precision, tio;s. ? the extended precision data format is also in conform- another factor in obtaining increased performance in ante with the ieee standard, but the standard does not the mc68882 is the odtimized fmove instructions for specify this format to the bit level whereas it does for ~r.: binary real data formats. these fmove instructions ex- \ single and double precision. the memory format on the :<21 ecute twice as fast as the corresponding fmove instruc- mc68882 consists of 96 bits (three long words), only 80 tions of the mc68881, the fmove instructions are also bits are actually used; the other 16 bits are for future mc= motorou br~/rov. 3 7 .,-, . ,. . .- . . . . . . . . . ,,. . ,, ,, ,,, - ,,. ,, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ,.. . . . . . ... . . . . . . . . . . . . . . . . ..- . . . . . . . . . table 1. exponent and mantissa sizes data exponent mantissa format bits bits bias single 8 23(tl) 127 double 11 52(+1) 1023 extended 15 64 16383 expandability and for long-word alignment of floating- point data structures. extended format hasa 15-bit ex- ponent, a 64-bit mantissa, and a l-bit mantissa sign. extended precision numbers are intended for use as temporary variables, intermediate values, or in areas where extra precision is needed, for example, a compiler might select extended precision arithmetic for evaluation of the right side of an equation with mixed sized data and then convert the answer to the data type on the left side of the equation. it is anticipated that extended pre- cision data will not be stored in large arrays due to the amount of memory required by each value. packed decimal string real data format the packed decimal data format allows packed bcd registers always contain extended precision values. all operands used are converted to extended precision by the mc68882 before a specific operation is performed, and all results are in extended precision. the use of ex- tended precision ensures maximum accuracy without p .,. 1$.,1 sacrificing performance. refer to figure 9 for a summary 4;3 of the memory formats for the seven data formats sup- ported by the mc68882. ~ ~*~.*. . . . . . . $,*, f !?}~{,?.(,!~tt., :*, ,. ;,~y ?..~j,, ~\$\,.. ~$., , ../,.? ~.:, the mc68882 instruction set ist&~~$~8&d into six major classes: ? 94 91 80 0 17-digit : : ~ : : ~ : jmantissa;!:~j~; packed decimal real . . . . . . . . . . :.. . . . ,.:$:.t. ~, *i,, ~~:~,~. ,.,,.,. *,. figure 9. mc68882 data format summary .?::$:$ ?..\..i:$\*.~~ .,* >,,, ~, >, ,, %*,$\$r. . . . . ., *,*\,>~\ .a*t&\ i::,, .st,, $. .,. >1> .,>> ,,, :~; o~a program. these moves are also useful at the start monadic operations and end of a procedure to save and restore the register monadic operations have one operand. this operand set of the calling routine, in order to reduce procedure may be in a floating-point data register, memory, or in call overhead, the list of registers to be saved or restored an mc68020 or mc68030 data register. the result is al- \ can be contained in a data register thus enabling run- ways stored in a floating-point data register. for example, time optimization by allowing a called routine to save as the syntax for square root is: few registers as possible, note that no rounding or ov- fsqrt. the mc68882 monadic operations available are as fol- the necessary condition checking and reports to the lows: fabs facos fasin fatan fatanh fcos fcosh fetox fetoxmi fgetexp fgetman fint flintrz flogio flog2 flogn flognpi fneg fsin fsincos fsinh fsqrt ftan ftanh ftentox ftst ftwotox mc68020 or mc68030 whether the condition is true or absolute value false. the mc68020 or mc68030 then takes the appro- arc cosine priate action. since the mc68882 and mc68020 or arc sine mc68030 are closely coupled, the floating-point branch r $~:: arc tanqent operations execute very quickly. q;. > hyperb&ic arc tangent the mc68882 conditional operations are: cosine fbcc branch hyperbolic cosine fdbcc decrement and branch,. ~$:<~ e to the x power fscc set according to coqqi~~~s e to the x power ?1 ftrapcc trap-on condition ~? $?! ? get exponent (with an opti~?~l~~&?#meter) get mantissa ,~* . /.j!:{&, where: ~:. ,+* ~ !.,*q: * ?,. integer part cc is one of the 32 floatind~@n$-~onditional test integer part (truncated) specifiers as given in~%~~~@? log base 10 **..*. . 1.$. ,fy log base 2 ?.,., ~ !?l.- >~/. :i::~ ,7.. ,} \;h \ ,,y ~\ log base e ~... <,.,, \ ~:???\%:., *;t log base e of(x + 1 ) table 2. ,@~fi,~?-point conditional negate ,e~;~~ specifiers sine ?..., simultaneous sine and cosine hyperbolic sine square root tangent hyperbolic tangent 10 to the x power test >;):.?. . f:.. 2 to the x power &;i ,ih;,~<+ \$y[.::\k, >.. ?~>? ~~ ..*: ,.,, . . . . dyadic operations .j,, ~.+is ~ ~,?:~ ::\. dyadic operations have two operands e~$~$~?~~ first operand is in a floating-point data regis\@y, %?~oryt or an mc68020 or mc68030 data registe~~?$:~~.:;~cond op- erand is the contents of a floating-p~~f$~~~% register. the destination is the same floating-p~$~%.~%ta register used for the second operand. for ex~&~l,~the syntax for float- *,w,, , , ing-point add is: i.. fadd. . . . ,. . . . miscellaneous instructions unique format word prevents a saved mc68881 context miscellaneous instructions include moves to and from from being restored into an mc68882 and vice versa. the status, control, and instruction address registers, also second, the bsun (branch or set on unordered), snan included are the virtual memory/machine fsave and (signaling not-a-number), operr (operand error), ovfl frestore instructions that save and restore the internal (overflow), dz (divide by zero) and inex (inexact result) state of the mc68882. floating-point exception handlers must have these min- fmove . . ..- table 3. coprocessor intetiace register selection a4-ao offset mdth type register oooox $00 16 read response ooolx $02 16 write control oolox $04 16 read save oollx $06 16 r~ restore oloox $08 16 ? (reserved) ololx $oa 16 write command ollox $oc 16 ? (reserved) olllx $oe 16 write condition 1 ooxx $10 32 rfi operand 101ox $14 16 read register select iollx $16 16 ? (reserved) 11 oxx $18 32 read instruction address illxx $lc 32 rr operand address when the mc68882 is configured to operate over an 8- bit data bus, the ao pin is used as an address signal for byte accesses of the coprocessor interface registers. when the mc68882 is configured to operate over a f16- or 32- bit system data bus, both the ao and the size pins are strapped high and/or low as listed in table 4. address strobe (as) this active-low input signal indicates that there is a valid address on the address bus, and both the chip select (cs) and read/write (r~) signal lines are valid. r . . . ~:- chip select (cs) .::. :y this active-low input signal enables the main processor access to the mc68882 coprocessor interface registers. when operating the mc68882 as a peripheral pro$essor, the chip select decode is system dependent (i.~~~j~$the chip select on any peripheral). ?..., .\\!.+?*: >} ,i,~ ?? ..$?s,*k. ~;, .?;.l\ .,,.\$, ~\...:~ read/write (r/~) ?%$,, *;>k:,, ?:3,. ?~ ~ ,h+.t.::~, . !, .? .t..i~ ..,! this input signal indicates the di~~8]o~#@y a bus trans- action (read/write) by the main~f~~~sbr. a logic high (1) indicates a read from the @8,@~, an~ a logic low (0) indicates a w~te to the ~~~8&the rn signal must be valid when as is ass@xl@+~j: ~..+ ?. **,?,)$.!+ . ?x., ,, \ -$: ~:<:~,.. ..,/ , data strobe (ds)?:xj~,~,t.$~ ,;~.>t,, . ,>+f, this active-lowin:~~~ignal indicates that there is valid data on the d~~~:~ys during a write bus cycle. ??, ~kese active-low, three-state output signals indicate ..?~,,c&hpletion of a bus cycle to the main processor. the i$$it,~@8882 asserts b~h the dsacko and dsacki signals table 4. system data bus size configuration *$rs$$upon assertion of cs. ?-l?+ if the bus cycle is a main processor read, the mc68882 ao size data bus ~ ,:? ~i$t ,$~$? asserts dsacko and dsacki signals to indicate that the .; ?>:,}, ? low 8-bit information on the data bus is valid. (both dsack signals .tt,. *>:.,. * ..* .,,, ,,.,,, low high may be asserted in advance of the valid data being placed 16-bi~$$?q$y ??? on the bus. ) if the bus cycle is a main processor write to .,?, . . . :. high high 3~*qk$;,.~? the mc68882, dsacko and dsacki are used to acknowl- .~~,;~y$. edge acceptance of the data by the mc68882. ,. ?\\.~j~.\ .?~:i,> ,,..:.. ,, ,4). > ? ?%;v, $~$ the mc68882 also uses dsacko and dsacki signals data bus (do through d31 ) ~~? ??~~ to dynamically indicate to the mc68020/mc68030 the this 32-bit, bidirectional, +~k~%%~bte bus serves as the ?port? size (system data bus width) on a cycle-by-cycle general purpose data,~~~h,~etween the mc68020/ basis, depending upon which of the two dsack pins are mc68030 and the mc~~&~.???regardless of whether the asserted in a given bus cycle, the mc68020/mc68030 as- mc68882 is operat~d a~$~?coprocessor or a peripheral sumes data has been transferred to/from an 8-, 16-, or 32-bit wide data port. table 5 lists the dsack assertions processor, all in~,@$@o,gessor transfers of instruction in- formation, op~r,~~d$$~ata, status information, and re- that are used by the mc68882 for the various bus cycles quests for $~~j~@?&ccur as standard m68000 bus cycles. over the various system data bus configurations. the mq@,*~will operate over an 8-, 16-, or 32-bit table 5 indicates that all accesses over a 32-bit bus syste~%at%~,bbs. depending upon the system data bus where a4 equals zero are to 16-bit registers, the mc68882 conj~@~~{a@n, both the ao and size pins are configured implements all 16-bit coprocessor interface registers on s~:~?t~a?lly for the applicable bus configuration. (refer to data lines d16-d31 (to eliminate the need for on-chip :$q~*ess bus (ao through a4) and size (size) for fur- multi plexers); however, the mc68020/mc68030 expects ?&#rdetails). 16-bit registers that are located in a 32-bit port at odd $$j word addresses (al = 1) to be implemented on data lines do-d i 5. for accesses to these registers when configured size (size) for 32-bit bus operation, the mc68882 generates dsack this active-low input signal is used in conjunction with signals as listed in table 5 to inform the mc68020/ the ao pin to configure the mc68882 for operation over mc68030 of valid data on d16-d31 instead of do-d15. an 8-, 16-, or 32-bit system data bus. when the mc68882 an external holding resistor is required to maintain is configured t~erate over a 16- or 32-bit system data both dsacko and dsacki high between bus cycles. in bus, both the size and ao pins are strapped high and/or order to reduce the signal rise time, the dsacko and low as listed in table 4. dsacki lines are actively pulled up (negated) by the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table 5. dsack assertions data bus a4 dsacki dsacko comments 32-bit 1 low low valid data on d31-do 32-bit o low high valid data on d31-d16 16-bit x low high valid data on d31-d16 or d15-do 8-bit x high low valid data on d31-d24,.d23-d16, d15-d8, or d7-do all x high high insert wait states in current bus cycle mc68882 following the rising edge of as or ds, and both dsack lines are then three-stated (placed in the high- impedance state) to avoid interference with the next bus cycle. reset (reset) this active-low input signal causes the mc68882 to initialize the floating-point data registers to non-signaling not-a-numbers (nans) and clears the floating-point con- trol, status, and instruction address registers. when performing a power-up reset, external circuitry should keep the reset line asserted for a minimum of four clock cycles after vcc is within tolerance. this as- sures correct initialization of the mc68882 when power is applied, for compatibility with all m68000 family de- vices, 100 milliseconds should be used as the minimum. when performing a reset of the mc68882 after vcc has been within tolerance for more than the initial ~ower-uo ~ ~~~.j, .:j;:::{:.jy<,:~:!l ~, time and must conform to minimum and m~~~~.~??pe- riod and pulse width times. *~. ? ~ ~~j,?~ ~?~ $..;.., ,w~\.:.\l~. ?:$w,. ,. ,<,,, ,*s.$.* ? y,, sense device (sense) ,,:,,? it,. .> ,k.:.:t.:, ,, .$ ~! *!v$ ,$~ this pin may be used optionally ~~~fi,$~ditional gnd pin or as as indicator to exte{~?~?$t~~dware that the mc68882 is present in the sys~$m$%~~ signal is internally connected to the gnd of t~:~~$~, but it is not necessary to connect it to the ext~w$$?ound for correct device operation. ifa pullup rp~~$~iwhich should be iargerthan 10 kohm) is conneqq~t~%~s pin location, external hard- .a*~j: ~ ,x~:,<,:i,. ware may sense, the~resence of the mc68882 in a sys- tem. . ~,~t~. ~$}.}. ~t:.,it ,$* !>:$;$. ,b~., $7::+ ~ower ~gc~j ~nd) ,.\q,~.,.. .*,:,,. ,~. ,,, thes%i~~ns provide the supply voltage and system ref- er%a$e iekl for the internal circuitry of the mc68882, care ..~~uf~ be taken to reduce the noise level on these pins time, the reset line must have an asserted p~lse width ,p,$~fi~ appropriate capacitive decoupling, which is greater than two clock cycles. for compatibility .*,. ?*>$*s ?~;$,::::b%?$: with all m68000 family devices, 10 clock cycles should i;,, -ho connect (nc) be used as the minimum. .,<..(*? ,$,$ clock (clk) ..,7,. ? !..!,$:,,,, i~,,!, .?*t. the mc68882 clock input is a ~l-com~#~w&~ignal that is internally buffered for development~~,th~ ?nternal clock signals, the clock input should ,qd~$:&~%fi:stant fre- quency square wave with no stretchi~~~$~$haping tech- niques required. the clock should q~t~ ~ated offat any .,:~:,?,? . . . ..sy. >.,? ... one pin of the mc68882 package is designated as a no connect (nc). this pin position is reserved for future use by motorola, and should not be used for signal routing or connected to vcc or gnd. signal summary table 6 provides a summary of all the mc68882 signals described in the above paragraphs. t!;:>\ <. signak<#a*ej?o \ mnemonic lnputioutput active state three state :~i:i\y address bus,~>?:$ ao-a4 input high ? { data bus ?$:$ **~~#f do-di 3 input/output high yes size ,%~~>)~ size input low ? ?~$?$s~tro be g input low ? , , ?&i,@s-elect m input low ? ~,t:,)...~ ,> ?@:j;~ ?:?%ad/write rim input high/low .$~,+,)?:., ~ \ ?~ 3 ? ?? ?$~? data strobe m input low ? .,t{,!~ ~.~ data transfer and size acknowledge dsacko, dsack1 output low yes reset reset input low ? clock clk input ? ? sense device sense input/output low no power input vcc input ? ? ground gnd input ? ? mc- br=/rev. 3 . . . . . . . . . . . . . . . ... ,, ... .,, .,.., . . . . . . , . . . . . . . . . . . . . . . . . . . . ,,, ..,. ,.? ,,, ,,. ., ,? ,.. motorola 13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interfacing methods mc68882/mc6801 o or mc68030 interfacing the following paragraphs describe how to connect the mc68882 to an mc68020 or mc68030 for coprocessor operation via an 8-, 16-, or 32-bit data bus, 32-bit data bus coprocessor connection figure 11 illustrates the coprocessor interface connec- tion of an mc68882 to an mc68020/mc68030 via a 32-bit data bus. the mc68882 is configured to operate over a 32-bit data bus when both the ao and size pins are con- i a16-a19 ~ decode i - v. size netted to vcc. fco-fc2 a- chip ? select e oecode ? vcc size a20-a31 a16-a19 a13-a15 a5-a12 a1-a4 ~ ~ ao 8 z e e 0 ~ e 0 r~ z z d24-031 ~ a1-a4 d24-d31 d16-d23 d8-d15 do-d? fco-fc2 016-d23 d8-d15 do-d7 dsacko dsack1 main processor clock d24-d31 d16-d23 08-015 do-d7 m d24-d31 d16-d23 ./,:, ,,. . ,,,, ,$:/; 16-bit data bus @+@oce&sor connection figure 12 ill.y~~~#?the coprocessor interface connec- tion of an m~m2 to an mc68020/mc68030 via a 16-bit data bu~i,~k~wc68882 is configured to operate over a 16-bit,@~d~~ bus when the size pin is connected to vcc, and. t~e ~0 pin is connected to gnd. the sixteen least- s~~k~?arit data pins (do-d15) must be connected to the j $:a~~~~en most-significant data pins (d1 6-d31 ) when the !&&8882 is configured to operate over a 16-bit data bus + main processor da-d15 do-07 =h dsacko osack1 \ ? coprocessor ~.e., connect do to d16, di to d17, . . . and d15 to d31). clock clock the dsack pins of the two devices are directly con- nected, although it is not necessary to connect the dsacko figure 13. 8-bit data bus coprocessor connection pin since the mc68882 never asserts it in this configu- ration. bus. the mc68882 is configured to operate over an 8-bit 8-bit data bus coprocessor connection data bus when the size pin is connected to gnd. the figure 13 illustrates the connect of an mc68882 to an twenty-four least-significant data pins (do-d23) must be mc68020/mc68030 as a coprocessor over an 8-bit data connected to the eight most-significant data pins (d24- motorou mc- 14 brw/rav. 3 ,., ,, . . . . . ...,,,. . . . . . . . ,,. - f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . d31) when the mc68882 is configured to operate over an when connected as a peripheral processor, the mc68882 8-bit data bus (i.e., connect do to d8, d16 and d24; di chip select (cs) decode, is system dependent. if the to d9, d17, and d25; . . . and d7 to d15, d23 and d31). mc68000 is used as the main processor, the mc68882 cs the dsack pins of the two devices are directly con- must be decoded in the supervisor or user data spaces, netted, although it is not necessary to connect the dsacki however, if the mc68010 is used for the main processor, pin since the mc68882 never asserts it in this configu- the moves instruction may be used to emulate any cpu ration. space access that the mc68020/mc68030 generates for coprocessor communications. thus, the cs decode logic mc68882-mc68000/mc68008/mc68010 interfacing for such systems may be the same as in an mc68020/ the following paragraphs describe how to connect the mc68030 system, such that the mc68882 will not-?hse any mc68882 to an mc68000, mc68008, or mc6801 o proces- ., ;*s.t::\~& part of the data address spaces. k};< ..n*.. sor for opertion as a peripheral via an 8- or 16-bit data ,,i#:*~? ,,.:; {$:, ~, ?,?.: ~.i bus. ~~ ,* ~$$, 8-bit data bus peripheral processor c,~~~f~8n 16-bit data bus peripheral processor connection figure 15 illustrates the connecti,~hjd~j~k mc68882 to an mc68008 as a peripheral proc~$@??r,@ver an 8-bit data figure 14 illustrates the connection of an mc68882 to <.~1.g, , !!*,*), bus, the mc68882 is configur~ tm~perate over an 8-bit an mc68000 or mc68010 as a peripheral processor over data bus when the size piq,,is??&&#nected to gnd. the a 16-bit data bus. the mc68882 is configured to operate eight least-significant d~ti$~~s (do-d7) must be con- over a 16-bit data bus when the size pin is connected to netted to the twenty:f~~~~~st-sig nificant pins (d8-d31 ) vcc, and the ao pin is connected to gnd. the sixteen when the mc68882a{,~.~~b@ figured to operate over an 8- least-significant data pins (do-di 5) must be connected to bit data bus (i,e,, q~@m?do to d8, d16, and d24; di to the sixteen most-significant data pins (d16-d31 ) when the d9, d17, and ~$; .?!:,* and d7 to d15, d23, and d31), the mc68882 is configured to operate over a 16-bit data bus dsacko pin$$,~~~ mc68882 is connected to the dtack (i.e., connect do to d16, di to d17, ,.. and d15 to d31). pin of th@ ,, . . . . . . . . . .- .,.:.... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .,. -.?, . . electrical specifications maximum ratings rating symbol value unit supply voltage vcc ?0.3 to +7.0 v input voltage ~n ?0.3 to +7.0 v operating temperature ta o to 70 ?c storage temperature t~tq ?55to +150 ?c thermal characteristics characteristic symbol value rating thermal resistance ? ceramic ?cm junction to ambient 9ja 33 junction to case 8jc 15 power considerations <,*,:b?+~ the total thermdk,g@wstance of a package (0.ja) can be the average chip-junction temperature, tj, in ?c can :.?. -. separated in,t$?{~&o components, ojc and eca, repre- be obtained from: senting th@.*q~#$i~efto heat flow from the semiconductor tj=ta+(pd06ja) (1) junctio,$.t$,th~ package (case) surface (ejc) and from the where: case tq $he+dutside ambient (oca). these terms are re- ta = ambient temperature, ?c lat@ b~she equation: 8ja = package thermal resistance, .ti.,.$,m ~ ~ s~, , . . . eja= 6jc+ 6ca (4) junction-to-ambient, oc/w j #??s$jc is device related and cannot be influenced by the pd = pint+ pi/0 3,j$&&r. however, 6ca is user dependent and can be min- pint = icc x vcc, watts ? chip internal power + .+,?! ~$t,:.,.. ,.,, . %,+$~tlmized by such thermal management techniques as heat pi/0 = power dissipation on input and output ? . :k. pins ? user determined ,,1 >:. .?:? . . . . . for most applications p1/o ac electrical characteristics ? clock input (vcc=5.o vdc* 570; gnd=o vdc; ta=o to 70c; refer to figure 16) 16.67 mhz 20 mhz 25 mhz 33.33 mhz num characteristic min max min max min max min max ?nit frequency of operation 8 16.67 12.5 20 12.5 25 16.7 33.33 mhz 1 cycle time 60 125 50 80 40 80 30 60 ns 2,3 clock pulse width (measured from 1.5 v to 1.5 v 24 95 20 54 15 59 14 66 q,s for 33 mhz) ..,?..,., ..:?,}*.. *,,i+i.,, 4,5 rise and fall times ? 5 ? 5 ? 4 ? 3$? , ,? ?f.:. ;,,, rs ~!?,~. a?>,, ,\$* (vcc=5.o vdc* 5%; gnd=o vdc; ta=o ~~@@$refer to figures 17, 18, and 19) ~1$ ,* $>\. *::>.? :. ?,, . ,,. ? ,.?*\\> ,. ,/ ns 7a6 ~ nega@&i~@yaddress invalid 10 ? 10 ? 5 ? 5 ? ns 89 ~%g~<$d to ~ asserted o ? o ? o ? o ? ns 8a9 ,.* %~*&ated to ~ asserted (read) o ? o ? o ? o ? ns q~ f,k. @ asserted to ~ asserted (write) 30 ? 25 ? 20 ? 15 ? ns ),~. y ~ i @_ ?~:;p as negated to ~ negated 10 ? 10 ? 5 ? 5 ? ns ~ ?~i<%x ~ negated to ~ negated 10 ? 10 ? 5 ? 5 ? ns ,, ? 10 r% high to ~ asserted (read) 15 ? 10 ? 5 ? 5 ? ns 10a rfi high to ~ asserted (read) 15 ? 10 ? 5 ? 5 ? ns iob r/~ low to ~ asserted (write) 35 ? 30 ? 25 ? 25 ? ns 11 ~ n_egated to r~ low (read) or ~ negated to 10 ? 10 ? 5 ? 5 ? ns r/w high (write) 11a ~ negated to r/~ low (read) or ~ negated to 10 ? 10 ? 5 ? 5 ? ns rfi high (write) ? continued ? u mc68882 motorola br~/rev. 3 17 ?--. *p8, !!!\,m,m ~., :,! . . . . . . . . ..-.. t.fo. t..! .,!r,,.j. >.,,.,, ryrtaw.w..-r. tw.,,l, t,,.., q, tm, f.7. --, yt,..,., .. ~,.!., . . . . . . . . . - ;., $-: ..!.,, ~,. . .,,-.,.-. 1 ..!... . . . . . . . . . ., :.....- ,. . . . . . .. ... ., ?, ,., ( :, ,, . .,. , .: ... . . . . . . . . ,,;, , . ...,..,:,:,..;., ,,,, . :: , ,.. ,, ...:., .< .. . . . . . . . ,.r.,,~. ! ~?--~,y,. ,- .,, , , ,1,.-. . .,..~.? :?.,~,.;l ..:,->*t ~, ,,, !,, ,t.. . . ,. ?:.. ,~.,: . . . ...7-.... (, ,?. ,, ,, ,, .,?., ... ,. ,1,, ,., , .. ,?:,.,. ;,,.. ,.. , ?, ?., ?,?. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ac electrical specifications ? read and write cycles (continued) 16.67 mhz 20 mhz 25 mhz 33.33 mhz num characteristic min max min max min max min max unit 12 ~ width asserted {write) 40 ? 38 ? 30 ? 23 ? ns r ~~. , 13 ~ width negated <:, , 40 ? 38 ? 30 ? 23 ? ns 13a4 = negated to ~ asserted 30 ? 30 ? 25 ? 18 ? ns 142 ~, ~ asserted to data-out valid) (read) ? 80 ? 60 ? 45 ? 15 ~ negated to data-out invalid (read) o ? o ? o ? o 16 ~ negated to data-out high impedance (read) ? 50 ? 30 ? 30 17 data-in valid to ~ asserted (write) 15 ? 10 ? 5 ? :$ &~~: ~ - ns 18 ~ negated to data-in invalid (write) 15 ? 10 ? 5 7 192 ~<:~ ?(~? ? n5 ? ? start true to dsacko and dsack1 asserted ? 50 ? 35 ? ,$ ?$~b,. i? 20 ns 19a7 dsacko asserted to dsacki asserted (skew) ?15 15 ?lo 10 ? ? 20 - $*., $:.10 ? ? 5 n5 dsacko or dsacki asserted to data-out valid ? 50 ? 43 ,j;~ :, ?. i ? mc= motorom brw/rev. 3 19 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . l + 21 ? t- 22 ? ? ? ~,,,,, ?\,, ,,. ;. ,, motorow mc- 20 br~/rev. 3 ,,, . ,,,,.,,- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . s1 ? s2 sw sw sw sw s3 s4 s5 mc- motorou brw/rev. 3 21 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . drive to 2.4 v clk a 0.8 v ~ orive j ~a+ to 0,5 v b + outputs(1) clk valid 2,0 v ? c2.0v valid output n 0,8v7 ~0,8v outputn+l ? -2.0 v + 0.8 v motorou mc= z brw/rev. 3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ?. , i pin assignments and mechanical data pin assignments r ~:$, pin grid array . ,j 0000000000 al r~ gnddsack1 d30 d29 d27 d26 d24 d22 0000000000 ?? a3 vcc cs dsacko d31 d28 d25 gnd d23 d21 00-0 000 ~ a2 ao vcc gnd d19 o. 0 00 ~a4 d20 d18 00 = gnd 00 d17 d16 00 00 nc vcc vcc gnd 00 0 q; reset gnd 000 0 d; %~&$ gnd clk gnd d9 ,,,:f:&:,>;,dli o 0 0 & o 0 0 q?v,q,,??0 vcc gnd gnd sense d2 d5 gnd\$v~ ?~l~ dll o 0 0 0 0 0 0<::.,0???0 0 vcc gnd do d1 d3 d4 ,,?}w6 ?~{~~ d8 gnd tdp view --- ~ d9 60 61 0 e- nc gnd reset gnd rl k mc- motorow brw/rev. 3 23 --- ,., ,. . ..<..,>,., . . . . . . . . . . . . . . ;., ,,. .,,,. . . . . . . . . . . . . . ... , , ,, .:,,, . . . . . . . . . . . . . . . . . . . . .? ---- . . . . . . . . . . . . . . . . . . . . . . . . . ,. ..,.. . . . . . . . .. :.? ?.. ,-t!t l . . . . . . . . . . . . . . . ...-.4. ..- ,. . . . . . . . . . . . . . .,. ,.. -, . . ,.,? ,, ?...- ,,, , .:, :, :,?, . ,!, . . . ,. ,.. .,. , :,.. ,, ,: ;?. , f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . - ? ,,. motorom 24 m~ br~/rev. 3 ., ..,. . . . . . . ,,. . . . . . . . ... .,,, . ,. . . . . . . . . . . . . . ,. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . fn suffix plastic leaded chip-carrier case 779-02 i l ?b + 0,18 (0,007) @ t n@p@ l&m@ ru [$1 o.18 (o.qq71 @ ] t n @-p@ l@m@ i d 7? a + 0.18 (0.0071 @ t l@-m@l n@-p@ ?r 1+]0.18 (0.007) @ \ t i l@m @l n@-p@] i i a 0.10 (0,004) ne i l\ i i u detail s ~ :,* :*... $? 0.48 0.013 0.019 f notes: 1. due to space limitation, case 779-02 shall be represented by a general (smalleri case outline drawing rather than showing all 68 leads. 2. datums -l., m-, -n-, and -p- determined where top of lead shoulder exit plastic body at molo parting line. 3, dim gl, true position to be measured at datum -t-, seating plane. 4, dim r and u do not include molo protrusion. allowable mold protrusion is 0.25 (0,010} per side, 5. dimensioning and tolera.ncing per ansi y14.5m, 1982. 6. controlling dimension: inch, m~ motorola brw/rev. 3 25 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . , . . . m68000 family standard ordering in formation,., note: consult factory for products requiring exte@d~erating temperatures or special processing. ~tf<.i?.< \.\, *:\ ?~:t~+ ..! motorola order number: .,) :,. , l&&ot&k~a???&serves the ,right to make changes witho:t f:rrher notice to any products herein to improve reliability, function or design. motorola ~~sr~ assume any imblhty ar!slng out of the application or use of any product or circuit described herein; neither does it convey any license u~er its patent rights nor the rights of others. motorola products are not authorized for use as components in life support devices or systems int%nded for surgical implant into the body or intended to suppo~ or sustain life. buyer agrees to notify motorola of any such intended end use whereupon motorola shall determine availability and suitability of its product orproducts for the use intended. motorola and@ are registered trademarks of motorola, inc. motorola, inc. is an equal employment opportunity:affi rmative action employer. literature distribution centers: usa: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. europe: motorola ltd.; european literature center; 88 tanners drive, blakelands milton keynes, mk145bp, england. j asia pacific: motorola semiconductors h.k. ltd.; po. box 80300; cheung sha wan post office; kowloon hong kong. n - m motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
Price & Availability of MC68882EI25A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |